• DocumentCode
    356787
  • Title

    Results on the fitness and population based fault tolerant approaches using a reconfigurable electronic device

  • Author

    Keymeulen, Didier ; Stoica, Adrian ; Zebulum, Ricardo ; Duong, Vu

  • Author_Institution
    Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    537
  • Abstract
    The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics. The fitness approach defines, in an explicit way, the faults that the component may encounter during its lifetime and evaluates the average behavior of the individuals. The population approach uses the implicit information of the population statistics accumulated by the genetic algorithm over many generations. The paper presents experiments done using both approaches on a fine-grained CMOS field programmable transistor array (FPTA) architecture for the synthesis of a fault-tolerant XNOR digital circuit. Experiments show that the evolutionary algorithm is able to find a fault-tolerant design for the XNOR function that can recover functionality when lost due to not a-priori known faults, by finding new circuit configurations that circumvent the faults. Our preliminary experiments show that the population approach designs a fault-tolerant circuit with better performance using less computation than the fitness based approach
  • Keywords
    CMOS digital integrated circuits; NOR circuits; circuit CAD; circuit reliability; evolutionary computation; fault tolerance; reconfigurable architectures; fault-tolerant XNOR digital circuit; fault-tolerant evolvable hardware design; fine-grained CMOS field programmable transistor array architecture; fitness based fault tolerant approach; genetic algorithm; implicit information; population based fault tolerant approach; population statistics; reconfigurable electronic device; Algorithm design and analysis; CMOS digital integrated circuits; Circuit faults; Circuit synthesis; Digital circuits; Evolutionary computation; Fault tolerance; Genetic algorithms; Hardware; Statistics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolutionary Computation, 2000. Proceedings of the 2000 Congress on
  • Conference_Location
    La Jolla, CA
  • Print_ISBN
    0-7803-6375-2
  • Type

    conf

  • DOI
    10.1109/CEC.2000.870343
  • Filename
    870343