Hardware implementation of a secure random number generator

This paper presents novel approaches to design and validation of a secure hardware Random Number Generator (RNG), Filtered-FCSR cascade, which is based upon the structure of Gollmann cascade. To further validate the security of the proposed RNG structure a more extensive check has been performed over many output bit sequences, using the US National Institute of Standard and Technology (NIST) SP 800-22 test suite. It is shown that this design holds a secure mathematical structure which can resist attacks, and meets known standards. Hardware implementation using an Altera Cyclone FPGA has been developed and results show such architecture is novel in being both secure and very highly efficient for hardware implementation.