High resolution digital-to-time converter for low jitter digital PLLs

We propose a Digial-to-Time Converter (DTC) that is capable of providing infinite-delay-over-time for application in low-jitter digital phase locked loops. The DTC is implemented using phase interpolation of quadrature phase high-speed clock signals with weight coefficients generated by direct digital synthesis. Novelty of the architecture lies in using (i) a slow-settling current steering DAC that provides low jitter at sampling clock; (ii) a current reuse mixer at the output of the DAC that saves power and improves linearity; and (iii) a folded architecture of low pass current-mode gyrator filter at the mixer output that allows sufficient voltage headroom. The proposed DTC, designed in 90 nm CMOS technology, achieves 1.85 ps in time resolution and consumes 2.2 mW of power from IV supply. To the best of our knowledge, the proposed architecture provides best resolution and linearity for a DTC capable of providing infinite-delay-overtime.