• DocumentCode
    3568611
  • Title

    Fused modulo 2n − 1 add-multiply unit

  • Author

    Tsoumanis, Kostas ; Pekmestzi, Kiamal ; Efstathiou, Constantinos

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece
  • fYear
    2014
  • Firstpage
    40
  • Lastpage
    43
  • Abstract
    Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n - 1 Add-Multiply (AM) operation. We incorporate in the design the direct recoding of the sum of two numbers in its Modified Booth (MB) form. Compared to the conventional design of first instantiating a modulo 2n - 1 adder and then, driving its output to a modulo 2n - 1 multiplier, the proposed fused AM design yields considerable reductions in terms of critical delay, area complexity and power consumption.
  • Keywords
    digital signal processing chips; multiplying circuits; residue number systems; AM design; DSP applications; MB form; area complexity; complex arithmetic operations; critical delay; digital signal processing applications; direct recoding; fused modulo 2n-1 add-multiply unit; modified booth form; power consumption; residue number system; Adders; Complexity theory; Delays; Digital signal processing; Encoding; Power demand; Modulo 2n − 1; RNS; addition; fused add-multiply unit; multiplication; residue number system;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICECS.2014.7049916
  • Filename
    7049916
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3568611