• DocumentCode
    3568615
  • Title

    A zero-crossing digital phase-locked loop architecture with hyperbolic nonlinearity for high Doppler environments

  • Author

    Salahat, Ehab ; Al-Qutayri, Mahmoud ; Al-Araji, Saleh R. ; Saleh, Hani

  • Author_Institution
    Coll. of Eng., Khalifa Univ., Abu Dhabi, United Arab Emirates
  • fYear
    2014
  • Firstpage
    56
  • Lastpage
    59
  • Abstract
    This paper presents a new Zero-Crossing Digital Phase-Locked Loop (ZC-DPLL) for frequency synchronization and tracking. The proposed hyperbolic Σ-Δ based ZC-DPLL has an improved time jitter by a factor of 6.4 and an extended lock-in range by a factor of sinh(π)/π. These significant improvements were achieved by introducing a hyperbolic nonlinearity and a modified Σ-Δ blocks to the original ZC-DPLL architecture. These intentionally added system blocks adapt the loop filter and hence result in extending the loop locking range and improving its time jitter. The proposed hyperbolic ZC-DPLL performs well in wireless communication systems with high Doppler shift that may cause the system to lose lock. The extensive simulation results of the new architecture under various conditions show the robustness of the new architecture in terms of lock-in range, acquisition time, and jitter.
  • Keywords
    Doppler effect; digital phase locked loops; sigma-delta modulation; Doppler shift; frequency synchronization; high Doppler environment; hyperbolic nonlinearity; hyperbolic sigma-delta based ZC-DPLL; zero-crossing digital phase-locked loop; Amplitude shift keying; Digital filters; Frequency synchronization; Jitter; Phase locked loops; Steady-state; Synchronization; Frequency Synchronization; Lock-in Range; Raised-Cosine; Sigma-Delta; Time Jitter; ZC-DPLL;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICECS.2014.7049920
  • Filename
    7049920