A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller

This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 × 0.36 mm². It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block The average settling time at 25 °C is 3 μs.