Analysis and modeling of oscillators with interference noise

Author

Shimizu, Shinji ; Mizuno, Junki ; Morishita, Shuei ; Hida, Koichiro ; Yoshimura, Tsutomu

Author_Institution

Grad. Sch. of Eng., Osaka Inst. of Technol., Osaka, Japan

fYear

2014

Firstpage

128

Lastpage

131

Abstract

In this paper, the influence of the external voltage noise on VCOs (voltage-controlled oscillators) is studied. The phase error is derived by using the impulse response of the oscillators. We found that the frequency properties of the noise sensitivity strongly depend on the circuit configuration of the VCO. We applied these results to the linear model of a PLL (phase-locked loop) and carried out a numerical simulation. The simulation result shows that the generation of the phase error depends on the timing of the impulse noise and the bandwidth of the PLL. The test chip for the verification is designed and fabricated in a standard CMOS process.

Keywords

CMOS integrated circuits; error analysis; impulse noise; phase locked loops; sensitivity analysis; transient response; voltage-controlled oscillators; CMOS process; PLL bandwidth; VCO; circuit configuration; external voltage noise; frequency properties; impulse noise timing; impulse response; interference noise; linear model; noise sensitivity; numerical simulation; oscillator analysis modeling; phase error; phase locked loop; test chip; voltage-controlled oscillators; Integrated circuit modeling; Interference; Noise; Phase locked loops; Sensitivity; Voltage-controlled oscillators; behavioral model; interference; phase-locked loop; voltage-controlled oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on

Type

conf

DOI

10.1109/ICECS.2014.7049938

Filename

7049938