Employing incremental sigma delta DACs for high resolution SAR ADC

Successive Approximation Register analog-to-digital converters (SAR ADC) have received increasing attention due to their direct benefit from technology scaling. However, while the achievable speed has been improved significantly, the reported effective resolutions are usually limited below 12 bits. This is mostly caused by the limited accuracy of the common implementation of the internal digital-to-analog converter (DAC) as charge redistribution switched-capacitor DAC. To remove this limitation, this paper proposes a novel approach to build the internal DAC in a SAR ADC as an incremental Sigma-Delta modulator (SDM). With its simple and low cost design the proposed scheme for the feedback DAC enables the design of power and cost efficient, high resolution SAR ADCs. The proposed DAC incorporates an incremental digital SDM followed by a semi-digital reconstruction filter, which approximates the ideal reconstruction filter for a third order digital SDM, with relaxed matching requirements. The proposed architecture is compared to other common high resolution ADC topologies.