Design of a high linearity Gm stage for a high speed current mode SAR ADC

An approach towards high speed current mode based SAR ADCs is presented in this paper. The main focus is placed on the design of a high-speed high-linearity transconductance (Gm) stage for operation in a current based SAR ADC. The Gm stage converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. Here, for high speed operation, large transconductance values are needed. Additionally, achieving high linearity over a wide input range requires linearization techniques, which increase the hardware effort and reduce the power efficiency. Thus, settling speed and linearity are the key determining factors for the design of a high-speed high-linearity Gm stage in a current based SAR ADC. Additionally, this paper presents an initial investigation of the Gm stage current settling under linear load. The theoretical analysis is compared against a schematic level implementation in a 1.2 V 90 nm CMOS technology. This Gm stage implementation is designed for an overall resolution of 10 bit in the current based SAR ADC over a Nyquist band from DC to 100 MHz.