A 160-GHz three-stage fully-differential amplifier in 40-nm CMOS

This paper presents a 160-GHz fully-differential power amplifier in 40-nm CMOS. A tapered gate-connection network was optimized which results in a reduction of the gate resistance and allows to achieve a maximum gain of 11.6 dB with a 3-dB bandwidth of 24 GHz from the three-stage amplifier. The measured saturated output power is 4.1 dBm and the measured 1-dB compression power is 1.5 dBm. The matching networks are implemented using on-chip transformers and slow-wave transmission lines. Differential and common-mode stability is obtained by adding cross-coupled capacitance to the differential pairs and series resistance to the bias network respectively. The amplifier core occupies an area of 0.063 mm² due to the compact design and the use of slow-wave transmission lines. With a supply voltage of 1.0 V, the amplifier consumes a DC current of 42 mA.