A 160-GHz three-stage fully-differential amplifier in 40-nm CMOS

Author

Van Thienen, Niels ; Reynaert, Patrick

Author_Institution

KU Leuven ESAT/MICAS, Leuven, Belgium

fYear

2014

Firstpage

144

Lastpage

147

Abstract

This paper presents a 160-GHz fully-differential power amplifier in 40-nm CMOS. A tapered gate-connection network was optimized which results in a reduction of the gate resistance and allows to achieve a maximum gain of 11.6 dB with a 3-dB bandwidth of 24 GHz from the three-stage amplifier. The measured saturated output power is 4.1 dBm and the measured 1-dB compression power is 1.5 dBm. The matching networks are implemented using on-chip transformers and slow-wave transmission lines. Differential and common-mode stability is obtained by adding cross-coupled capacitance to the differential pairs and series resistance to the bias network respectively. The amplifier core occupies an area of 0.063 mm² due to the compact design and the use of slow-wave transmission lines. With a supply voltage of 1.0 V, the amplifier consumes a DC current of 42 mA.

Keywords

CMOS integrated circuits; coupled transmission lines; differential amplifiers; optimisation; slow wave structures; transformers; CMOS; bias network; common-mode stability; cross-coupled capacitance; current 42 mA; differential-mode stability; frequency 160 GHz; frequency 24 GHz; gate resistance; on-chip transformers; size 40 nm; slow-wave transmission lines; tapered gate-connection network; three-stage fully-differential amplifier; voltage 1 V; CMOS integrated circuits; Gain; Logic gates; Metals; Semiconductor device measurement; Stability analysis; Transmission line measurements; CMOS; Fully-differential; G-band; Power amplifier; Transformer-coupled; mm-Wave;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on

Type

conf

DOI

10.1109/ICECS.2014.7049942

Filename

7049942