Compressing code for embedded systems

The size of the embedded software is increasing at a rapid pace. Often, the task of designing hardware that meets a lot of functionality needed in software became a challenging process and it needs more time for projecting. Then, the compression code is a way to reduce this problem. This paper presents an innovative and efficient approach to code compression. Our method reduces code size by up to 31% (including all extra costs). We performed simulations and analyzes, using the applications from benchmark MiBench and use two embedded processors (ARM and MIPS). Our method is orthogonal to approaches that take into account the particularities of a given instruction set architecture, becoming an independent method for any specific architecture. We have implemented the decompressor using VHDL and FPGA and we obtained only one clock from decompression process.