Supply-voltage down conversion for digital CMOS designs

This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.