A 79dB THD CMOS low power THA circuit using pseudo differential source follower and common-mode management

This paper presents a CMOS track-and-hold (THA) circuit using pseudo differential source follower. Without using high gain high power consumption operational amplifier, the input analog signal sampled with bottom plate sampling technique and held at the gate of the source follower PMOS transistor. The harmonic distortion of the source follower is improved by eliminating the short channel effect of the PMOS transistor and reducing the input dependence of the gate-to-drain voltage (VGD). To solve the poor common-mode rejection ratio (CMRR), the proposed THA introduces one additional switching phase which can cancel the input common-mode voltage before the signal is held. The propsoed SHA circuit is fabricated using 0.18 CMOS process and the measurement result shows more than 79dB total harmonic distortion (THD) and significant CMRR under 200 MHz sampling frequency consuming only 10 mW power.