Distributed asynchronous controllers for clock management in low power systems

In digital electronic systems, the power consumption is nowadays a standard non-functional specification. Therefore the design of such complex SoCs in the nanoscale technologies is now constrained by many parameters such as the energy consumption and the robustness to process variability. Basically the implementation of a gated clock structure is a good way to limit the dynamic power consumption. Nevertheless, this needs extra computation to determine which part of the circuit has to be switched off. Moreover, the insertion of asynchronous interfaces instead of synthezising gated clock in an existing system is one way to quickly provide a robust framework for power reduction. In this paper, we introduced a novel methodology-based on a set of simple distributed asynchronous controllers - to efficiently implement gated clock at the system level. This approach has been successfully applied to an AXI bus-based system with a negligible hardware cost compared to the equivalent fully-synchronous system. The obtained results indicate that the proposed technique can have a significant impact on the power consumption with a low redesign cost.