Low-power, high-data-rate, BPSK demodulator for implantable biomedicai applications

A novel ultra-low power non-coherent BPSK demodulator for biomedical implants is presented. The proposed demodulation technique is based on utilizing a delayed and digitized form of the input signal for the detection of the received data and also for retrieving a synchronized clock signal. The BPSK demodulator circuit proposed in this work is capable of operating at a carrier frequency of 10 MHz with a data-rate-to-carrier-frequency (DRCF) of up to 100%. Designed and simulated in a 0.18-μm standard N-Well CMOS technology, the circuit consumes 27.2μW@1.8V. The proposed demodulation concept was also realized on a proof-of-concept prototype circuit board.