A simulated-annealing-based approach for timing-constrained flexibility-driven routing tree construction

As the complexity of VLSI circuits increases, the routability problem becomes more and more important in modern VLSI design. In general, the flexibility improvement of the edges in one routing tree has been exploited to release the routing congestion and increase the routability in the routing stage. In this paper, given an initial routing tree, based on the definition of the routing flexibility in a SRT and the timing-constrained location flexibility of the Steiner-point in one Y-type wire, the simulated-annealing-based approach is proposed to obtain a better timing-constrained flexibility-driven SRT by reassigning the feasible locations of the Steiner-points in a SRT. The experimental results show that our proposed STFSRT algorithm can obtain 43%∼173% improvement on the measure of total routing flexibility for the tested benchmark circuits.