• DocumentCode
    3568936
  • Title

    Static variable ordering in ZBDDs for path delay fault coverage calculation

  • Author

    Kocan, Fatih ; Gunes, Mehmet ; Thornton, Mitchell A.

  • Author_Institution
    Southern Methodist Univ., Dallas, TX, USA
  • Volume
    1
  • fYear
    2004
  • Abstract
    Zero-suppressed binary decision diagrams (ZBDDs) are data structures that represent sets efficiently and they have recently been suggested for use in nonenumerative path delay fault (PDF) coverage calculations. Many heuristics have been proposed to order variables (representing primary inputs) in ZBDDs to avoid size explosion; however, in ZBDD-based PDF coverage calculations, the variables represent the nets in a circuit, not the circuit primary inputs. This fact motivates us to investigate new ordering strategies since the number of nets in a circuit is relatively large as compared to the number of primary inputs. Several new static ordering heuristics are proposed based on structural properties of the circuit undergoing PDF coverage calculations and are evaluated. The experimental results show that the new heuristics we propose greatly reduce the size of the ZBDDs.
  • Keywords
    VLSI; binary decision diagrams; combinational circuits; fault location; logic testing; sequential circuits; VLSI circuits; combinational circuits; data structures; logic testing; path delay fault coverage calculation; sequential circuits; static variable ordering heuristics; structural properties; zero suppressed binary decision diagrams; Circuit faults; Circuit testing; Data structures; Delay; Flip-flops; Logic testing; Programmable logic arrays; Programmable logic devices; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
  • Print_ISBN
    0-7803-8346-X
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2004.1354036
  • Filename
    1354036