• DocumentCode
    3569029
  • Title

    PESE: an efficient partition-based electrical simulation environment

  • Author

    Kim, Y.G. ; Dharchoudhury, A. ; Kang, S.M. ; Kim, K.H.

  • Author_Institution
    CAE Group, Samsung Electron. Co., Kyungki, South Korea
  • Volume
    1
  • fYear
    1995
  • Firstpage
    57
  • Abstract
    Due to the performance limitations of electrical level circuit simulators, the number of design circuits that cannot be analyzed but need to be simulated at the electrical level are increasing. Hence, extensive research has been carried out with the aim of improving simulation performance for large and complex circuits. This paper introduces a new environment for electrical level simulation with high performance. PESE uses circuit partitioning based on the channel connectedness, in conjunction with a standard electrical simulator like SPICE, to provide a greater simulation speed with less memory requirement while maintaining the desired level of electrical accuracy. The size of circuits PESE can handle is not limited, and the speedup is expected to grow with the circuit size while having much less memory space requirement. Several benchmark circuits have been tested and the results show that PESE provides accurate simulation capability with a speed and memory space advantage
  • Keywords
    VLSI; circuit analysis computing; PESE; channel connectedness; circuit partitioning; circuit simulators; partition-based electrical simulation environment; Analytical models; Benchmark testing; Circuit simulation; Circuit testing; Computational modeling; Convergence; Equations; Logic gates; Performance analysis; SPICE; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
  • Print_ISBN
    0-7803-2972-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1995.504377
  • Filename
    504377