Digital pulse frequency modulation for switched capacitor DC-DC converter on 65nm process

DC-DC converter is one of the most important building blocks in any System-on-Chip (SoC). DC-DC converter has the functional capabilities to supply various voltage levels to various loads of the chip in a way to achieve high power efficiency. Pulse Frequency Modulation is considered as the main control technique for voltage regulation of the Switched Capacitor DC-DC power converter. This paper proposes a design of a digital Pulse Frequency Modulation using Verilog-HDL and verified on 65nm low power process technology. The design includes the generation of the non-overlapping clock by the ring oscillator and the dead time circuit instead of the default clock. PFM has a total power of 7μW, area of 46.4μm² and a slack time of 0.5ns.