32 dB gain W-band LNA in 28 nm bulk CMOS

Author

Pepe, Domenico ; Zito, Domenico

Author_Institution

Tyndali Nat. Inst., Cork, Ireland

fYear

2014

Firstpage

694

Lastpage

697

Abstract

A high gain low noise amplifier for radiometrie applications in the W band has been designed in 28 nm bulk CMOS technology and characterized experimentally. The design of pads, inductors, capacitors, coplanar waveguides and interconnect lines has been carried out by means of electromagnetic simulations. The parasitic effects of the transistor layout have been evaluated by means of electromagnetic simulations and hand calculations. The amplifier consists of six cascode stages with interstage conjugate matching for the maximum power transfer; the first stage includes also an inductive degeneration for the input integrated matching. Measurement results show a peak gain of 32 dB and a noise figure of 5.3 dB at 91 GHz.

Keywords

CMOS integrated circuits; capacitors; coplanar waveguides; inductors; integrated circuit layout; low noise amplifiers; millimetre wave amplifiers; radiometry; transistors; W-band LNA; bulk CMOS technology characterization; capacitor design; cascode stages; coplanar waveguide design; electromagnetic simulations; frequency 91 GHz; gain 32 dB; hand calculations; high gain low noise amplifier; inductive degeneration; inductor design; input integrated matching; interconnect line design; interstage conjugate matching; maximum power transfer; noise figure 5.3 dB; pad design; parasitic effects; radiometric applications; size 28 nm; transistor layout; CMOS integrated circuits; Gain; Inductors; Layout; Microwave radiometry; Semiconductor device modeling; Transistors; 28 nm; CMOS; LNA; Radiometer; W-band;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on

Type

conf

DOI

10.1109/ICECS.2014.7050080

Filename

7050080