Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes

CNFETs have potentials to replace CMOS devices due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. The presence of metallic Carbon Nanotubes (m-CNTs) is one of the major fabrication challenges as it negatively impacts the performance, power and yield of CNFET-based circuits. We verified on larger circuit a newly developed capacitance-based Logical Effort (LE) model for ideal CNFETs, and adopted it to estimate the delay of CNFET-based circuits with the variation of the number of tubes in the channel. The variation results from the initial presence of metallic tubes, which are next removed by one of the known removal techniques. Our model results in fairly accurate delay estimation with maximum error less than 5% for a set of tested CNFET circuits.