Hierarchical design flow for heterogenous systems using Pareto front interpolation

This paper presents a framework enabling the predictive synthesis of heterogeneous systems using a hierarchical approach. Sub-blocks are represented by interpolation functions approximating their Pareto-optimal performance trade-off, which in turn constrain the design space at the system level. This guarantees feasible and optimal designs at every abstraction level, enforces reuse and allows the constitution of IP libraries. Moreover, the interpolation functions are language-agnostic, which eases the integration of several domains in the same design flow. Experimental results in the design of an Optical Network-on-Chip show the potential of the framework.