Neuro control of a PFC rectifier for harmonic reduction at partial loads

Boost PFC converters using conventional control techniques exhibit the problem of significant harmonic content in the input current at partial loads. This leads to mains pollution as well as nonunity power factor. Though, some techniques exist to mitigate this problem. The computation of the algorithms involved require complex numerical algorithms which are challenging especially for high switching frequencies. This paper introduces a neuro control system, in order to overcome this problem. Because of its parallel structure, such a neuro control is ideal for implementation on FPGAs or ASICs. Simulations verify that the proposed neuro control scheme reduces the harmonics at partial load significantly. The third harmonic, for instance, has been reduced from 33.3% to 0.72% at partial load. A hardware investigation reveals that the parallel computation of the neuro control requires a calculation time of 160-250 ns on state-of-the-art FPGAs.