Simulation and implementation of an analog VLSI pulse-coupled neural network for image segmentation

Author

Matolin, Daniel ; Schreiter, J?¶rg ; Sch?¼ffny, Ren?© ; Heittmann, Arne ; Ramacher, Ulrich

Author_Institution

Dept. of Electr. Eng. & Inf. Technol., Dresden Univ. of Technol., Germany

Volume

2

fYear

2004

Abstract

We present a massively parallel VLSI realization of a pulse-coupled neural network for image segmentation. The network comprises 128 × 128 simple nonleaky integrate-and-fire (IAF) neurons with self-organizing inter-neural connections. The prototype implementation also contains analog memories for image storing and a digital readout circuit using an address-event-representation (AER) protocol. The chip has been designed in an Infineon 0.13 μm standard CMOS technology.

Keywords

CMOS memory circuits; VLSI; analogue storage; image segmentation; neural nets; parallel memories; parallel processing; 0.13 micron; CMOS technology; Infineon; address-event-representation protocol; analog VLSI; analog memory; digital readout circuit; image segmentation; image storage; integrate-and-fire neurons; prototype implementation; pulse-coupled neural network; self-organizing inter-neural connections; Biological neural networks; Biomembranes; CMOS technology; Circuits; Frequency; Humans; Image segmentation; Neural networks; Neurons; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354177

Filename

1354177