On a 3D recursive motion estimation algorithm and architecture for digital video SoC

Motion estimation algorithm plays a crucial role in video coding/processing and accounts for almost one quarter of the gate count or area in many digital video system-on-a-chip (SoC) due to its computational intensive nature. In this paper, we present a complexity-reduced three dimensional (3D) motion estimator (ME) which reduces the number of search candidates and hence gate count significantly. Moreover, by virtue of its recursive architecture, hardware estimated sum of absolute differences (SAD) and motion vectors (MV) can be passed backed to the embedded DSP processor for image segmentation, resulting in efficient software/hardware partition in SoC designs. In addition, the calculated SAD´s can also be further analyzed by the embedded CPU for rate control in video coding. Alleviating traditional ME artifacts such as illumination, this motion estimator with segmentation capabilities is readily applicable to video object planes (VOP) processing in levels higher than the advance simple profile in MPEG4, H.264 and motion compensated format converters such as deinterlacers and scan-rate converters.