Netlist partitioning for FPGA-based run-time reconfiguration

This paper demonstrates the feasibility of using automated netlist partitioning to improve the performance of a single FPGA run-time reconfigurable system. Run-time reconfiguration (RTR), an important model for computing, can outperform other computing solutions for some applications and exhibit high architectural flexibility. The performance of RTR is heavily influenced by circuit partitioning. While partitioning procedures to enhance RTR have been previously explored, their nature remains poorly understood. A partitioning system has, therefore, been designed and implemented in software to interface functional circuits to an industry standard graph partitioning heuristic and to study its performance. Experimental results demonstrate that a 103 gate, low-power DCT implementation with 105 nets may be bipartitioned with an interpartition bandwidth of 3 nets.