Clock synchronization errors in circuits: models, stability and fault detection

Author

Lorand, C?©dric ; Bauer, Peter H.

Author_Institution

Dept. of Electr. Eng., Notre Dame Univ., IN, USA

Volume

2

fYear

2004

Abstract

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems.

Keywords

asynchronous circuits; asynchronous transfer mode; clocks; delays; fault diagnosis; state-space methods; synchronisation; telecommunication switching; active clock edges; asynchronously switching systems; clock signal propagation; clock synchronization errors; fault detection; fault identification; global system properties; high speed circuits; high speed systems; multiple sub-systems; propagation delays; state-space approach; synchronously switching system; time instants; Circuit faults; Circuit stability; Clocks; Electrical fault detection; Equations; Fault diagnosis; Propagation delay; Switches; Switching systems; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354206

Filename

1354206