Isomorphic structured synthesis of Half Adder and Full Adder

In this paper we present a new method for synthesis of Half Adder (H.A.) and Full Adder (F.A) Units. The synthesis is based on Graph Oriented Realization (GOR). GOR uses BDD and generates another graph called Cut Set Graph. This graph is then simplified and compiled for technology mapping. In the synthesized circuits, we show that there is an isomorphism between 2-input´s AND (Carry) with 2-input´s XOR (Sum) in H.A. and between 3-input´s (Carry) with 3-input´s XOR (Sum). Level Restoration is accomplished by output drivers. Each unit is simulated by HSPICE.