Author :
Thean, A.V.-Y. ; Yakimets, D. ; Huynh Bao, T. ; Schuddinck, P. ; Sakhare, S. ; Bardon, M. Garcia ; Sibaja-Hernandez, A. ; Ciofi, I. ; Eneman, G. ; Veloso, A. ; Ryckaert, J. ; Raghavan, P. ; Mercha, A. ; Mocuta, A. ; Tokei, Z. ; Verkest, D. ; Wambacq, P. ;
Abstract :
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
Keywords :
SRAM chips; field effect transistors; logic circuits; nanowires; GAA transistors; LFET; SRAM design; VFET device; circuit influences; contact placement; device density scaling; gate placement; gate-all-around; layout efficiency; parasitics; vertical nanowire logic circuits; vertical transistors; Capacitance; Layout; Logic gates; Random access memory; Resistance; Transistors; Wires;
