Design of a 8 bit current-steering DAC for a GSM transmitter

Author

Marin, Mihai-Eugen ; Brinzei, Catalin ; Constantinescu, Florin ; Gheorghe, Alexandru ; Ursac, Iulian

Author_Institution

Electr. Eng. Dept., Univ. Politeh. Bucharest, Bucharest, Romania

fYear

2014

Firstpage

1

Lastpage

5

Abstract

An 8 bit 1GSPs DAC targeting transmitters for mobile communications terminals has been implemented in 0.18μm TSMC technology. A correction scheme is used for the current sources in order to achieve a SFDR greater than 50dB after layout parasitic extraction in the 10MHz bandwidth. The simulated values for INL/DNL are 0.268 LSB and 0.377 LSB respectively. A 5+3 segmented architecture is used in order to reduce glitches. At 1Gbps sample rate, the total power consumption is estimated to be 15 mW on 2.5V/1.5V analog/digital supply voltages with a total die area of 0.23 mm².

Keywords

cellular radio; digital-analogue conversion; mobile radio; radio transmitters; DNL error; GSM transmitter; INL error; LSB; SFDR; TSMC technology; analog supply voltage; current steering GSP DAC design; differential nonlinearity error; digital supply voltage; digital to analog converter; glitch reduction; integral nonlinearity error; layout parasitic extraction; least significant bit; mobile communication terminal; spurious free dynamic range; total power consumption; Bandwidth; Calibration; Computer architecture; Decoding; Layout; Microprocessors; Transistors; Calibration; Current steering DAC; Digital to analog converter;

fLanguage

English

Publisher

ieee

Conference_Titel

Fundamentals of Electrical Engineering (ISFEE), 2014 International Symposium on

Print_ISBN

978-1-4799-6820-6

Type

conf

DOI

10.1109/ISFEE.2014.7050565

Filename

7050565