RAM tests for safety-related architectures: A first approach

Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.