Reliability and technology scaling beyond the 10nm node

At the device level the rate of errors, SER, has been declining for SRAM, and more recently also for logic flip-flops (FF). The introduction of the FinFET has resulted in a further reduction in SER by about an order of magnitude compared to an equivalent planar structure due to a reduction in charge collection associated with the restricted fin geometry. Upsets due to thermal neutrons and muons are negligible compared to fast neutrons for FinFETs. Upsets also occur in combinational (random) logic circuits, and recent studies suggests this component of SER can be as large as that for unprotected FF at GHz frequencies. Due to the limited volume of Si available for particle interactions, GAA structures might be expected to be exhibit similar SER as FinFETs. However, high mobility channels present concerns because lower band gap energies coupled with higher carrier mobility will exacerbate SER despite the inherently robust FinFET or GAA geometry.