Title :
A cost-efficient hardware architecture of deblocking filter in HEVC
Author :
Xin Ye ; Dandan Ding ; Lu Yu
Author_Institution :
Zhejiang Provincial Key Lab. of Inf. Network Technol., Zhejiang Univ., Hangzhou, China
Abstract :
This paper presents a hardware architecture of deblocking filter (DBF) for High Efficiency Video Coding (HEVC) by jointly considering system throughput and hardware cost. A hybrid pipeline with two processing levels is adopted to improve system performance. With the hybrid pipeline, only one 1-D filter and single-port on-chip SRAM are used. According to the data dependence between neighbouring edges, a shifted 16×16 basic processing unit as well as corresponding filtering order is proposed. It reduces memory cost and makes the DBF friendlier to work in a coding/decoding system. The proposed hardware architecture is synthesized under 0.13um standard CMOS technology and result shows that it consumes 17.6k gates at an operating frequency of 250MHz. Consequently, the design can support real-time processing of QFHD (3840×2160) video applications at 60 fps.
Keywords :
CMOS integrated circuits; SRAM chips; decoding; pipeline processing; video coding; 1-D filter; DBF; HEVC; QFHD; basic processing unit; coding system; complementary metal oxide semiconductor; cost-efficient hardware architecture; deblocking filter; decoding system; frequency 250 MHz; high efficiency video coding; hybrid pipeline; memory cost reduction; processing level; quad full high definition; single-port on-chip SRAM; size 0.13 mum; standard CMOS technology; static random-access memory; video application; Filtering; Hardware; Pipeline processing; Pipelines; Random access memory; Throughput; Video coding; HEVC; cost-efficient; deblocking filter; hardware architecture; hybrid pipeline;
Conference_Titel :
Visual Communications and Image Processing Conference, 2014 IEEE
DOI :
10.1109/VCIP.2014.7051541
