DocumentCode
3571355
Title
Priority-Based Conflict Resolution for Hardware Transactional Memory
Author
Yamada, Ryohei ; Hashimoto, Koshiro ; Tsumura, Tomoaki
Author_Institution
Nagoya Inst. of Technol., Nagoya, Japan
fYear
2014
Firstpage
433
Lastpage
439
Abstract
Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively as long as there is no conflict on shared variables. On HTMs, which are the hardware implementations of TM, if a speculative execution of a transaction fails, the re-execution of the transaction should wait a period prescribed by a back off algorithm to avoid further conflicts. However, the performance of HTM may be decreased drastically by wastefully long back off periods. To address this problem, in this paper, we propose a new algorithm to set a value called Priority on each transaction, and the transaction which should be aborted is selected according to Priority instead of the initiated time of transactions. The result of the experiment shows that the execution time of HTM is reduced 59.9% in maximum, and 11.2% in average with 16 threads.
Keywords
concurrency control; multi-threading; multiprocessing systems; storage management; system recovery; transaction processing; HTM; back off algorithm; deadlock; hardware transactional memory; lock-based thread synchronization technique; lock-free synchronization; multicore processors; parallel programming; priority-based conflict resolution; speculative transaction execution; Coherence; Hardware; Instruction sets; Memory management; Message systems; Synchronization; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Computing and Networking (CANDAR), 2014 Second International Symposium on
Type
conf
DOI
10.1109/CANDAR.2014.47
Filename
7052222
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