Integration of Algorithms in Silicon

A system design approach based on the use of algorithm-specific integrated circuits is presented. This approach is illustrated with the examples of a 2-D image recognition system and a 1000 word speech recognition system which have recently been built. These systems demonstrate that the use of algorithm-specific chips leads to an enormous reduction in the size and hardware cost while providing computational performances on the order of several hundred MOPS on a single printed circuit board. Silicon assembly techniques are described which have been used for rapid prototyping of the algorithm-specific chips in these systems. It is shown that a set of common techniques and principles can be used for automatic layout generation of chips for widely differing algorithms resulting in a very low prototyping cost for these devices.