DocumentCode
3571751
Title
4Mb DRAM Circuit Features
Author
Kilmer, C. ; Bronson, T. ; Clinton, M. ; Kosson, J. ; Morency, D. ; Morrish, J. ; Newhart, R. ; Parent, R. ; Plouffe, R. ; Tewarson, D.
Author_Institution
IBM General Technology Division, Essex Junction, VT 05452, USA
fYear
1987
Firstpage
61
Lastpage
64
Abstract
An experimental 4Mb CMOS DRAM is described. Technology evolution, coupled with innovative circuit techniques, has led to a dense high-performance design. This paper illustrates some of the technology trade-offs and circuit features that were incorporated to facilitate fabrication on an existing manufacturing line.
Keywords
CMOS technology; Capacitance; Capacitors; Coupling circuits; Dielectric substrates; Fabrication; Noise reduction; Pulp manufacturing; Random access memory; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-state Circuits Conference, 1987. ESSCIRC '87. 13th European
Print_ISBN
3800715341
Type
conf
Filename
5434950
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