• DocumentCode
    3572013
  • Title

    Associative Control for Fault-Tolerant CMOS/SOS RAM-s

  • Author

    Haraszti, T.P.

  • Author_Institution
    Newport Beach Research Center, Hughes Aircraft Company, Newport Beach, California 92663, U. S. A.
  • fYear
    1981
  • Firstpage
    194
  • Lastpage
    198
  • Abstract
    A novel associative iterative circuit controls redundancy of large (16K bit-IMbit) CMOS/SOS memories. Yield optimization as function of defect density is combined with high speed - power performance. The circuit implementation for a 16K bit selftesting RAM adds only 2 nsec to access time, 1.5 mw to operating power and 0.6mm2 to silicon area.
  • Keywords
    Associative memory; CMOS technology; Fault tolerance; Fault tolerant systems; Hardware; Integrated circuit yield; Military standards; Random access memory; Redundancy; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 1981. ESSCIRC '81. 7th European
  • Print_ISBN
    3800712385
  • Type

    conf

  • Filename
    5435030
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3572013