Title :
Optimization of the Oxide-Isolated Transistor Structure for ECL Masterslice LSI´s
Author :
Masaki, A. ; Harada, Y. ; Ikeda, T.
Author_Institution :
Central Research Laboratory of Hitachi, Ltd., Tokyo, Japan
Abstract :
This paper discusses optimization of the oxide-isolated transistor structure for high speed ECL LSI´s. It is shown that, contrary to general expectation, higher performance can be achieved by using a ``non-walled´´ rather than a ``walled´´ emitter structure.
Keywords :
Capacitance; Contact resistance; Delay estimation; Delay systems; Laboratories; Large scale integration; Logic arrays; Logic circuits; Logic design; Wiring;
Conference_Titel :
Solid State Circuits Conference, 1977. ESSCIRC '77. 3rd European
