Modelling of Impact Ionization Current for LDD SOI MOSFETs

The impact ionization phenomenon in submicron LDD SOI MOSFETs is investigated using devices with body terminals. It is shown that in order to accurately model the impact ionization current for submicron LDD SOI MOSFETs, it is necessary to account for the voltage drop on the parasitic source-and-drain series resistances and for the gate-voltage dependent saturation field in the expression for the maximum channel electric field Em. It is demonstrated that the plot of IIMP/(IDEm) versus 1/Em is a single straight line for a given technology. In addition, method to extract the effective length of the saturation region is developed and extrapolation for shorter channel length devices is made.