DocumentCode
3573570
Title
200 mm DUV Lithography : Material and Process Optimization Application to 0.25 μm CMOS Technology
Author
Vinet, F. ; Buffet, N. ; Le Cornec, Ch. ; Lerme, M. ; Morand, Y. ; Mourier, T. ; Previtali, B. ; Paniez, P.J.
Author_Institution
GRESSI - LETI - CEA - Technologies Avanc?ƒ?©es - DMEL - CENG, 17 rue des Martyrs - 38054 Grenoble - Cedex 9, France
fYear
1995
Firstpage
123
Lastpage
126
Abstract
In order to achieve 0.25 μm CMOS devices with industrial transfer capability, a 8" DUV lithography cell has been installed, including a 5500/90 ASM-L DUV stepper and a TEL Mark 8 track. An original physico-chemical screening test, based on DSC, allows us to select optimized DUV positive materials regarding to delay, environment and substrate sensitivity. Process optimization with selected materials has been performed and implemented on 0.25 μm CMOS technology. Process latitudes as well as electrical results are presented.
Keywords
CMOS process; CMOS technology; Delay effects; Lithography; Optical materials; Resists; Temperature; Thermal resistance; Tin; Windows;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
Print_ISBN
286332182X
Type
conf
Filename
5435996
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