Title :
Optimizing the Natural MOSFETs in a 0.5μm Dual Poly Gate CMOS Process for 1V Mixed-Signal Applications
Author :
Bazarjani, Seyfi S. ; MacElwee, Tom ; Snelgrove, Martin
Author_Institution :
Department of Electronics, Carleton University, Ottawa, Ontario, Canada K1S 5B6. E-mail: seyfi @bnr.ca, seyfi @doe.carleton.ca
Abstract :
A IV analog CMOS technology is developed as a subset of a 0.5μm n+/p+ dual poly gate CMOS process. In this process, "natural" threshold voltage MOSFETs are optimized to have a Vt of about 200mV set by well implants. Process architecture, SUPREM3 simulations, and some measured data are presented.
Conference_Titel :
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
