High speed cellular array computer realizations for low power applications

In this paper a design method for building high speed array computers on a single chip is demonstrated with two example realizations. The key idea in the method is that an array computer can be built using reusable, relatively simple building blocks. All necessary memory is distributed among processing units. The number of processing units in the array computer is selected based on speed requirements, yielding a low power, small die area realization. Two different measured array processor realizations designed using the method are depicted.