Test data compression using Hamming Encoder and Decoder for system on chip (SOC) testing

As per Moore´s Law the growth of transistors in VLSI (Very Large Scale Integration) chip is doubled for every 18 months. Due to this rapid improvement, testing the VLSI integrated circuit for fault free conditions requires large duration of times. Hence this research paper going to propose the data compression technique using Hamming Encoder and Decoder to reduce the test time with small area overhead on chip. The novel methodology also reduces the switching activity between the modified test inputs which lead us to reduce the test power dissipation during testing. The estimation of area overhead is also determined through implementing the additional hardware component of novel circuit with the Field Programmable Gated Array (FPGA) SPARTAN III kit using XILINX ISE Design Suite 14.7 version tool. The entire hardware component of the chip is described using Hardware Description Language (HDL) Verilog. The estimation result shows as its required only minimum amount of hardware component approximately 5% is added to the chip.