DocumentCode :
3574374
Title :
A high linearity folded cascode Low Noise Amplifier for wireless receivers
Author :
Kukde, Anand A. ; Kumaravel, S. ; Venkataramani, B.
Author_Institution :
Dept. of ECE, NIT Trichy, Trichy, India
fYear :
2014
Firstpage :
1344
Lastpage :
1348
Abstract :
In wireless receivers, linearity is one of the performance metrics that needs to be addressed while designing LNAs. Modified Derivative Superposition (MDS) technique is one of the methods proposed in the literature to improve linearity. In the literature, Folded Cascode (FC) Low Noise Amplifiers (LNA) are proposed for low voltage and low power Radio Frequency Integrated Circuits (RFIC). In this paper, FC LNA adapting MDS technique (FC-MDS) is designed and implemented using UMC 0.13 μm RFCMOS process to operate at 900 MHz. From the simulation results, it is found that the proposed FC-MDS LNA achieves a Power Gain of 13.7 dB, Noise Figure of 1.1 dB, IIP3 of +7.77 dBm, and the S11 of -27dB. The designed LNA consumes 6.19 mW power. The Figure of Merit of the proposed LNA is higher by a factor of 1.2 to 6.5 than those of other cascode LNAs reported in the literature.
Keywords :
CMOS integrated circuits; low noise amplifiers; low-power electronics; radio receivers; radiofrequency amplifiers; radiofrequency integrated circuits; FC LNA; FC-MDS technique; RFIC; UMC RFCMOS process; frequency 900 MHz; gain 13.7 dB; high linearity folded cascode; low noise amplifier; low power radio frequency integrated circuits; modified derivative superposition technique; power 6.19 mW; size 0.13 mum; wireless receivers; CMOS integrated circuits; Gain; Impedance matching; Linearity; Noise figure; Radio frequency; Transistors; LNA; Modified Derivative Superposition; folded cascode; linearity; narrowband;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuit, Power and Computing Technologies (ICCPCT), 2014 International Conference on
Print_ISBN :
978-1-4799-2395-3
Type :
conf
DOI :
10.1109/ICCPCT.2014.7054929
Filename :
7054929
Link To Document :
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