A low power encoder for a 5-GS/s 5-bit flash ADC

A low power high speed encoder is proposed for a 5-GS/s 5-bit flash analogue-to-digital converter (ADC). The designing of a thermometer code to binary code is one of the bottlenecks in achieving high speed. The modus operandi involved in this process is that an encoder circuit translates the thermometer code into the gray code to reduce the effect of meta-stability and reduction of bubble errors. And also that low power and high speed encoder is designed by deploying a new logic design style to implement conversion of the thermometer code to binary code through differential cascade voltage switch logic (DCVSL). However the encoder proposed is designed by using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.5 V. The simulating results thus obtained is shown for sampling frequency of 5-GS/s and the average power dissipation of 23.29 μW.