Reconfigurable router design for Network-on-Chip

The Network-on-Chip (NoC) is a new interconnection method, able to integrate a large number of IP cores while maintaining a high communication bandwidth between them. The NoC is made of a number of routers that are interconnected to each other. The router may homogeneous or heterogeneous. Homogeneous router means the router in which each channel can have a same buffer size. Heterogeneous router means the router in which each channel can have a different buffer size. To obtain high flexibility and improve performance, MPSoCs will combine different types of processor cores and data memory units of different sizes, leading to heterogeneous architecture. But setting the buffer size at design time may lead to high power dissipation. So in this paper we go for reconfigurable router architecture. Actually the reconfigurable router is a heterogeneous router, but using reconfiguration technique, it is possible to dynamically change the buffer depth to each channel, in accordance with the necessity of the application and that increasing the power efficiency of the system. Here analyzed the average power consumption by CMOS 90nm standard cell library using the Synopsys Design Compiler tool. The reconfigurable router architecture while reaching the same performance as that of the homogeneous architecture, obtained a reduction in power consumption of 6.898% in the worst case, and of 70.73% for the best case analyzed. Also the proposed router architecture obtains 80.8% of power reduction when compared with the ViChaR router architecture.