Title :
A novel modulo 2n + 1 fused multiply-adder unit for secured VLSI architectures
Author :
Reddy, N. Sainath ; Ravindra, J.V.R.
Author_Institution :
Vardhaman Coll. of Eng., Hyderabad, India
Abstract :
There is increase in computer performance exponentially in past few decades which led to demand in low power and high speed arithmetic circuits which is highly challenging in designing of such kind of circuits. The Fused Multiply Add (FMA) is one of the most efficient designs from the arithmetic designs. This paper presents a novel FMA which is implemented by using modulo 2n + 1 adder and multiplier to achieve low power and high speed. The synthesis is carried out in RTL Complier using TSMC 130nm, 90nm, 65nm and 40nm technology files. In order to show the confidence of the proposed FMA it has been compared with existing one FMA. The results show that the proposed FMA has better performance in terms of delay, power and area.
Keywords :
VLSI; adders; floating point arithmetic; integrated circuit design; logic design; multiplying circuits; RTL complier; TSMC technology; VLSI architectures; fused multiply-adder unit; modulo 2n + 1 adder; modulo 2n + 1 multiplier; size 130 nm; size 40 nm; size 65 nm; size 90 nm; Adders; Computer architecture; Computers; Conferences; Delays; Standards; Very large scale integration; arithmetic logic structures and VLSI; floating point; fused multiply add; modulo 2n+1 addition and multiplication;
Conference_Titel :
Circuit, Power and Computing Technologies (ICCPCT), 2014 International Conference on
Print_ISBN :
978-1-4799-2395-3
DOI :
10.1109/ICCPCT.2014.7055038
