An optimized software implementation of the HEVC/H.265 video decoder

In this paper an optimized implementation of the HEVC video decoder is shown. The solutions developed to support the new features of HEVC are shown together with the achieved performance. The HEVC decoder complexity has been evaluated and the most demanding modules have been optimized exploiting SIMD instructions. Even though the here described concepts have a general value, the effectiveness of the proposed solutions has been verified on the ARM architecture. The selected architecture is ARM Cortex A9 with NEON SIMD extension. We will demonstrate that the resulting real-time HEVC software decoder can decode 720p (1280x720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.