Designing customized MIPS soft-core and configuring it at run time

Soft-core processor´s implemented on an FPGA are now days becoming very economical. These can be customized according to special needs and demands. Customization according to the application can be done using soft-core´s. But there exists a lot of overhead in reimplementing and downloading the core again to the FPGA, if in case any changes are required in the code. Hence a new technique to overcome this drawback is proposed here. This system is made up of three vital blocks. First is the soft-core UART. Second is the tool for writing assembly code at the user end. Third is the processor coded in verilog on an FPGA. The GUI will compile the assembly code and will send it through UART to the FPGA, where the processor is implemented. This way the processor can be loaded at run time.