Title :
Bounding the Worst-Case Execution Time of Static NUCA Caches
Author :
Yiqiang Ding ; Wei Zhang
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Commonwealth Univ., Richmond, VA, USA
Abstract :
Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET) accurately and safely. In this paper, we develop a WCET analysis approach to consider the effects of static NUCA caches on WCET.
Keywords :
cache storage; computer architecture; multiprocessing systems; real-time systems; WCET analysis approach; multicore processors; nonuniform cache architecture; real-time systems; static NUCA caches; uniform access time; wire delays; worst-case execution time; Delays; Equations; Mathematical model; Multicore processing; Program processors; Real-time systems;
Conference_Titel :
High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014 IEEE Intl Conf on
Print_ISBN :
978-1-4799-6122-1
DOI :
10.1109/HPCC.2014.193
